1. Field of the Invention
The present invention relates to a printed circuit board (PCB), and more particularly, to a PCB having an impedance-matched strip transmission line.
2. Description of the Related Art
High-speed memory devices are used in many applications. A package test is used for the assessment of the high-speed memory devices. In the package test, a plurality of memory devices are simultaneously tested in order to reduce manufacturing costs. To this end, a divider formed by using branch patterns of a strip transmission line on a test board is used. In the case of low-speed memory devices, desired data can be input or output by using the divider. However, in the case of the high-speed memory devices, since a reflection wave is generated due to an impedance mismatch in the strip transmission line and a signal delay is caused due to the reflection wave, desired data cannot be accurately input or output by using the divider.
FIG. 1 is a cross-sectional view illustrating a method of controlling impedance matching of a strip transmission line 120 in a conventional printed circuit board (PCB) 100. Referring to FIG. 1, an upper ground layer 110 is disposed above the strip transmission line 120, and a lower ground layer 150 is disposed below the strip transmission line 120. The strip transmission line 120 has a line width w1, and the PCB 100 has a thickness h1. In FIG. 1, ‘d11’ denotes a distance between a top surface of the strip transmission line 120 and a bottom surface of the upper ground layer 110, and ‘d12’ denotes a distance between a bottom surface of the strip transmission line 120 and a top surface of the lower ground layer 150. An electric field 130 is generated between the strip transmission line 120 and the upper and lower ground layers 110 and 150, and a magnetic field 140 is generated around the strip transmission line 120.
An impedance Zo of the strip transmission line 120 is determined by the thickness h1 of the PCB 100, a dielectric constant of a dielectric layer (not shown) surrounding the strip transmission line 120, and the line width w1 of the strip transmission line 120. The impedance Zo of the strip transmission line 120 increases as the thickness h1 of the PCB 100 increases. However, since a total thickness of a multi-layer PCB assembly increases as the thickness h1 of the PCB 100 increases, manufacturing processes are complicated and signal characteristics are degraded. The impedance Zo of the strip transmission line 120 increases as the dielectric constant of the dielectric layer decreases. However, since the dielectric constant of the dielectric layer is dependent on a material of which it is formed, there is a limitation in controlling the impedance Zo of the strip transmission line 120 by using the dielectric constant of the dielectric layer.
Since there is a limitation in controlling the impedance Zo of the strip transmission line 120 by using the dielectric constant of the dielectric layer and the thickness h1 of the PCB 100, a method of controlling the impedance Zo of the strip transmission line 120 by using the line width w1 of the strip transmission line 120 is often used. The impedance Zo of the strip transmission line 120 is expressed byZo=sqrt L/C}  (1).
The impedance Zo of the strip transmission line 120 is determined by a capacitance C and an inductance L. The impedance Zo increases as the capacitance C decreases, and increases as the inductance L increases. The capacitance C is determined by the distances d11 and d12 between the strip transmission line 120 and the upper and lower ground layers 110 and 150. The inductance L is determined by the line width w1 of the strip transmission line 120. That is, the capacitance C is determined by the electric field 130 whereas the inductance L is determined by the magnetic field 140. Accordingly, as the distances d11 and d12 between the strip transmission line 120 and the upper and lower ground layers 110 and 150 increase, the capacitance C increases, thereby decreasing the impedance Zo. As the line width w1 of the strip transmission line 120 decreases, the inductance L increases, thereby increasing the impedance Zo.
However, there is a limitation in increasing the impedance Zo by reducing the line width w1 of the strip transmission line 120. In particular, in order to increase the impedance Zo, branch transmission lines are realized as fine patterns with a reduced line width, thereby making it difficult to match impedances between the branch transmission lines.
Also, as the number of package balls or pins increases, the number of unit PCBs stacked on the multi-layer PCB assembly increases. As the number of the unit PCBs increases, the total thickness of the multi-layer PCB assembly increases. In order to reduce the total thickness of the multi-layer PCB assembly, the thickness of each of the unit PCBs should be minimized. As the thickness of each of the unit PCBs decreases, the distances d11 and d12 between the strip transmission line 120 and the upper and lower ground layers 110 and 150 decrease, thereby increasing the capacitance C and decreasing the impedance Zo.
FIG. 2A is a graph illustrating simulation results of a strip transmission line including two branch lines. FIG. 2B is a graph illustrating simulation results of a strip transmission line including four branch lines. Referring to FIGS. 2A and 2B, a reflection wave is generated in the strip transmission line due to an impedance mismatch in the branch lines and a transmission signal is delayed due to the reflection wave, thereby degrading the eye diagram characteristics of the transmission signal. In particular, it can be seen from FIGS. 2A and 2B that as the number of branch lines increases, the eye diagram characteristics are further degraded.